1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor integrated circuit device.
2. Related Art
In modern large scale semiconductor integrated circuit devices (hereinafter referred to as “LSIs”), a scale reduction of node diffusion layers of memory cells is achieved by miniaturization and/or reducing operating voltage, and the resistance to the soft-error problem, in which the information accumulated in the node diffusion layer is typically inverted, becomes a problem. It is known that electron-positive hole pairs are generated in the substrate by alpha particles or cosmic ray-origin neutrons generated from a package or a wiring material of a LSI, and a few carriers flow into the node diffusion layer to change the electric potential of the diffusion layer, thereby causing the soft-error. Further, since secondary ion generated by a nuclear reaction (nuclear crushing reaction) of neutron and silicon helps generating about 10-folds electron-positive hole pairs in comparison with the case of alpha particles, the soft error, which may induce the electric potential inversion of the general logic circuit in addition to memory cell, may be caused.
Countermeasures for such soft-error are known, such as increasing the node capacity of the memory cell as described later, or providing a barrier layer such as, for example, deep N wells enclosing a P well, which isolates the substrate surface from the substrate body, in order to avoid introducing carriers generated by the radioactive ray into the node diffusion layer.
On the other hand, in certain types of devices such as SRAM cell, the PN isolation spacing is reduced due to the miniaturization to provide larger capacity of the parasitic bipolar transistor, and thus there is a room of improving the latch-up resistance. Although the latch-up resistance in the conventional technology caused by the source voltage-originated trigger (trigger of the break-down of the PN junction or the break-down between SDs of a MOSFET) is gradually improved by lowering the operating voltage of the LSI in recent years, there is still a room for further improving other problems such as external noise and the like.
As countermeasures for the latch-up problems, technologies of reducing resistance of well/substrate (for example, providing a retrograde well or a lower resistance substrate) or providing dense number of the contacts for well electric potential and substrate electric potential, are known.
In such circumstances, a technology for simultaneously improving the soft-error resistance and the latch up resistance is disclosed in Japanese Patent Laid-Open No. JP-A-H10-70250 (1999), in which a lower concentration impurity layer is formed on an underlying layer of well formed on the principal surface of a semiconductor substrate and the impurity profile of the well/low concentration impurity layer/substrate is optimized. Another technology of changing the impurity density in a well of a semiconductor device having triple-well structure according to the required function is disclosed in Japanese Patent Laid-Open No. JP-A-2001-291779. Although these technologies are effective in solving the soft-error and latch-up problems by optimizing the nature of the substrate/well impurity, there is no description therein on how the electric potential of the substrate/well is drawn, and thus there is still a room for further providing an improvement in view of the latch-up resistance.
On the other hand, Japanese Patent Laid-Open No. JP-A-2003-60071 discloses a technology, in which a soft-error is prevented by providing a deep well layer (buried layer) as an interlayer under the N well/P well, which are formed on the semiconductor substrate. FIGS. 8A and 8B are figures for describing this type of technology, in which FIG. 8A is a plan view, and FIG., 8B is a schematic cross-sectional view along line E—E. Further, an enlarged cross-sectional view of the portion along line F—F of FIG. 8A is shown in FIG. 9. In these figures, MCs, which are sectioned by chain lines in FIG. 8A, is a 1-bit area of CMOS type SRAM cells, and P wells 202 and N wells 203 are provided on the silicon substrate 201. Gate electrodes 209 of NMOSFET and PMOSFET, which compose SRAM cell, are respectively formed on these wells, and both of the N+ diffusion layer 208 and the P+ diffusion layer 207 are formed in each well. Here, the gate electrodes 209 are not shown in FIG. 8B. Buried N wells 206 are formed over the entire surface of the layer underlying the aforementioned P well 202 and the N well 203. Further, a P+ diffusion layer 212 of the P well electric potential junction 204 is disposed for the aforementioned P well 202, and a N+ diffusion layer 213 of the N well electric potential junction 205 is disposed for the aforementioned N well 203. Here, the numeral number 214 indicates an interlayer insulating film, 215 indicates a contact electrode and 216 indicates a metal line. In such configuration, introduction of minor carriers generated in the substrate into each of the diffusion layers 207 and 208 of memory cells is inhibited by comprising the buried N well 206, thereby improving the soft-error resistance.
However, since such configuration provides electric connections for the P wells 202 by disposing P well electric potential junction 204 in every several memory cells (every bit), effective resistances of the P wells 202 is increased, and thus it is subjected to provide insufficient constitution in view of the latch-up resistance. Thus, in Japanese Patent Laid-Open No. JP-A-2003-60071, a buried P well is formed (not shown) between the P well 202 and N well 203 and the buried N well 206 disposed underlying thereof, and power feeding to the P well is conducted through the buried P well. Therefore, such configuration reduces the effective resistance of the P well, and thus is effective in improving with latch-up resistance. Nevertheless, providing the buried P well promotes a difficulty in escaping electron generated in the P well toward the direction to the deep portion of the substrate, and in this respect, an advantageous effect obtained by the countermeasures for the soft-error problem, in which the number of electric charge collected to the node diffusion layer is diminished, is adversely reduced.
On the other hand, U.S. Pat. No. 6,472,715 discloses technologies for improving the soft-error resistance by forming N well, which is adjacent to P well, to a deep region of the substrate, or alternatively by composing the deep N well that is a type of a N well, a lower region of which is extended to a lower region of the P well. Although there is no description on the latch-up countermeasures in this technology, it is presumed that the structure thereof is that the P well is partially in contact with the P-type substrate, and, in turn, the electric potential of the P well is also supplied from the substrate, resulting in improving the latch-up resistance. However, the improvement may be difficult in the structure such as memory cell, in which the MOSFETs are packed therein in the example of the disclosed technology, due to the transverse diffusion caused during the high-energy ion implantation. Further, in all the prior art disclosures listed above, there is no description on the optimization of substrate/well structure for the purpose of providing countermeasures for the soft-error of peripheral circuit (logic circuits except memory cell).
Here, it is generally known that the silicon-on-insulator (SOI) structure simultaneously provides improvements in both the soft-error resistance and the latch-up resistance. However, it is difficult to adopt the SOI substrate to the commercial production, because of the higher price of the SOI substrate, the difficulty in decreasing the size of the memory cell due to the necessity for the body contact in order to inhibit the operation of the parasitic bipolar device, the problems on the manufacturing process specified to the SOI substrate (e.g., silicidation is difficult) or the like.
It has now been discovered that, in the conventional LSI, when the impurity-containing layer is formed on the layer underlying the well to completely isolate the well from the substrate, resulting in improving the soft-error resistance, the trade-off is that the latch-up countermeasure easily becomes to be insufficient, since the manner of drawing the well electric potential/substrate electric potential is not optimum. On the other hand, when the well is partially in contact with the substrate to improve the latch-up resistance, insufficient countermeasures for the soft-error is provided since insufficient isolation of the well is provided.